該題鏈接：https://hdlbits.01xz.net/wiki/Cs450/gshare

這題主要是看不懂題目，沒法理解題目意思，而且對cpu的gshare預(yù)測分支不了解，所以做不出來。

當(dāng)train_valid=1時，PHT的位置由train_pc與train_history異或得到，而PHT的值則是由狀態(tài)機或者說由train_taken來決定。狀態(tài)機是之前題目中的飽和計數(shù)器，當(dāng)狀態(tài)是11或10時，會決定predict_taken為1. predict_taken的值有PHT的狀態(tài)決定。

其中寄存器代碼編寫與上題差不多。

module top_module(

??? input clk,

??? input areset,

?

??? input? predict_valid,

??? input? [6:0] predict_pc,

??? output predict_taken,

??? output [6:0] predict_history,

?

??? input train_valid,

??? input train_taken,

??? input train_mispredicted,

??? input [6:0] train_history,

??? input [6:0] train_pc

);

??? reg pht1[127:0],pht0[127:0];//定義128個1位寄存器pht1

??? wire [6:0]ad,ad2;

???

??? assign predict_taken=pht1[ad2];

??? assign ad=train_history^train_pc;

??? assign ad2=predict_history^predict_pc;

??? always@(posedge clk or posedge areset)begin

??????? if(areset)

??????????? for(int i=0;i<128;i++)begin

??????????????? pht1[i]=0;pht0[i]=1;end

??????? else if(train_valid&train_taken)begin

??????????? if({pht1[ad],pht0[ad]}==2'b11)

??????????????? {pht1[ad],pht0[ad]}<=2'b11;

??????????? else

??????????????? {pht1[ad],pht0[ad]}<={pht1[ad],pht0[ad]}+1;

??????? end

??????? else if(train_valid&~train_taken)begin

??????????? if({pht1[ad],pht0[ad]}==2'b00)

??????????????? {pht1[ad],pht0[ad]}<=2'b00;

??????????? else

??????????????? {pht1[ad],pht0[ad]}<={pht1[ad],pht0[ad]}-1;

??????? end//之前的飽和計數(shù)器

??? end

???

??? always@(posedge clk or posedge areset)begin

??????? if(areset)

??????????? predict_history<=0;

??????? else if(train_mispredicted & train_valid)

??????????? predict_history <= {train_history[5:0],train_taken};

??????? else if(predict_valid )

??????????? predict_history <= {predict_history[5:0],predict_taken};?

??? end

?

endmodule